TFTs have been employed in driving circuits of display devices such as OLED displays and LCD displays, and are being developed for improving their characteristics. Emergence of large-sized and high definition displays require these TFTs to have large current driving performance. Recently, TFT made of a crystallized semiconductor film, e.g. polycrystalline silicon or micro crystallite silicon, as an active layer is attracting attention.
As crystallization process for semiconductor films, high temperature process using temperature of 1000 degrees Celsius or more has been established. Recently, low temperature process using temperature of 600 degrees Celsius or less is being developed. The low temperature process can reduce manufacturing cost because this process does not require a use of expensive substrate such as quartz having an excellent heat resistance.
The laser annealing which uses a laser beam for heating attracts attention as one method of the low temperature process. In this method, a laser beam is irradiated on a non single crystal semiconductor film (amorphous silicon or polycrystalline silicon) which is formed on a heat-resistant insulating substrate such as glass substrate, and the semiconductor film is melted as a result. The semiconductor film is then crystallized during a cooling process. Using this crystallized semiconductor film as the active layer (channel domain), TFT is formed integrally. The crystallized semiconductor film has a high mobility carrier, and this improves the performance of TFTs.
As the structure of these TFTs, a bottom-gated structure having a gate electrode disposed under a semiconductor layer is mainly used. Japanese Patent Application Publications JP2001-028486A1 and JP2009-229941A1 describe the examples of such TFTs.
JP2001-028486A1 describes a method of first forming a wiring (electrode) connected to a transistor on a substrate, and then forming a planarized insulation film (an interlayer insulation film) made of photosensitive polyimide by spin coat method so that the film covers the wiring (electrode). Next, a connection hole (contact hole) is formed on the planarized insulation film using lithography method. An organic EL device, which is being connected to the wiring through the connection hole, is then formed on the planarized insulation film.
JP2009-229941A1 describes a protective insulation film layered on a second metal layer (electrode) and a planarized insulation film (an interlayer insulation film) layered on the protective insulation film each having a contact hole for inserting a connecting contact which electrically connects the second metal layer and an anode electrode (lower electrode). The contact hole has a cone-shape that is convexed downward so that the inner surfaces of the protective insulation film and the planarized insulation film are connected without a step.